FIG. 1 shows a prior art dual thread CPU 102 coupled to a first thread interrupt controller 104 and a second thread interrupt controller 106. FIG. 2 shows the execution of threads where CPU 102 has alternating cycles devoted to each thread as shown in 108. As can be seen in FIG. 2, each subsequent cycle is directed to an alternate thread, such that both threads THD1 110 and THD2 112 receive equal processing time. FIG. 3 shows the execution of a first thread THD1 116 as well as an interrupt THD1-INT 120, along with second thread THD2 118 and second thread interrupt THD2-INT 122. The time diagram 114 shows the roughly equal time devoted to processing the thread programs THD1 116 and THD2 118, as well as the thread interrupts THD1-INT 120 and THD2-INT 122.
FIG. 4 shows the effect of a disproportionate number of interrupts on a first thread T1 126 with the interrupts, noted as THD1-INT 130. The processing diagram 124 of FIG. 4 shows one cycle of first thread program THD1 126, and a first and second THD1-INT 402 and 404, while bandwidth is available in THD2 128.
U.S. Pat. No. 6,971,103 shows an inter-thread interrupt processor where one thread can assert an interrupt to a different thread using a thread identifier. Provision is made for only a single interrupt, which is cleared upon service.
U.S. Pat. No. 6,275,749 shows a memory system for use in context switching when servicing interrupts for a multi-thread processor.
U.S. Patent Application 2005/0102458 describes a priority encoder for use in a multi-thread processor which prevents the inversion of priority caused by interrupts of different priorities which arrive on one thread while another thread is executing.
U.S. Pat. No. 6,061,710 describes an interrupt handling system which initiates a new thread to handle new interrupt requests.